CN102789990A - Manufacturing technology for super-junction device with shallow slot source electrode structure - Google Patents
Manufacturing technology for super-junction device with shallow slot source electrode structure Download PDFInfo
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- CN102789990A CN102789990A CN2012102929653A CN201210292965A CN102789990A CN 102789990 A CN102789990 A CN 102789990A CN 2012102929653 A CN2012102929653 A CN 2012102929653A CN 201210292965 A CN201210292965 A CN 201210292965A CN 102789990 A CN102789990 A CN 102789990A
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Abstract
The invention relates to a manufacturing technology for a super-junction device with a shallow slot source electrode structure. The manufacturing technology comprises the following steps: after injecting ions into a P-type area, injecting high-energy boron ions into the P-type area by using a contact-hole photo-etching plate mask, thereby forming a P+ area buried layer structure; after preparing a polycrystalline silicon gate structure, injecting low-energy arsenic ions in a self-aligning mode, thereby forming a N+ source area on the upper side of a P+ area buried layer; depositing a BPSG (Boro Phospho Silicate Glass) dielectric layer; forming a contact hole by using the contact-hole photo-etching plate mask and etching silicon, thereby forming a shallow slot; and passing through the N+ source area and entering into the P+ area, thereby forming a U-shaped P+ area. According to the manufacturing technology, the length of a base electrode of a parasitic NPN transistor is reduced, so that the resistance of the base electrode is reduced, the difficulty in opening the parasitic NPN transistor is increased and the avalanche energy of a power device is increased. Only five photo-etching plates, namely, a P pillar photo-etching plate, a P-type area photo-etching plate, a polycrystalline silicon gate photo-etching plate, a contact-hole photo-etching plate and a metal photo-etching plate, are required, so that the manufacturing cost of the technology is greatly lowered.
Description
Technical field
The invention belongs to semiconductor device and technology and make the field, be specifically related to the manufacture craft of the ultra junction device of a kind of shallow slot source electrode structure.
Background technology
POWER VD MOS device will obtain higher puncture voltage; Epitaxial loayer drift region that just must be thicker and lower doping content; Thereby conducting resistance can sharply increase along with the increase of puncture voltage, receives the constraint of this " silicon limit " and can't further reduce for the conducting resistance of conventional structure power device.The engineer David J. Coe of PHILIPS Co. in application United States Patent (USP) in 1988 (High voltage semiconductor device [P]. US Patent 4; 754; 310. low-doped drift layer is as the method for Withstand voltage layer in the PN junction structure replacement conventional power device that 1988.), the proposition employing replaces in horizontal high-voltage MOSFET first.1993; The Chen Xing assist in education of University of Electronic Science and Technology is awarded and has been proposed in vertical power device (especially vertical MOS FET) with the thought of a plurality of PN junction structures as drift layer; (Xingbi Chen; Semiconductor power devices with alternating conductivity type high-voltage breakdown regions [P]. US Patent 5; 216,275. 1993.), and this structure be referred to as " compound buffer layer " (Composite Buffer Layer).Nineteen ninety-five, and the United States Patent (USP) of the J. Tihanyi application of Siemens Company (Tihanyi J. Power MOSFET [P]. US Patent 5,438 215.1995.), has proposed similar thinking and application.The people such as scholar Tatsuhiko of Japan in 1997 have proposed " ultra knot " (Superjunction) theory under the summary to above-mentioned notion.Theoretical in conjunction with ultra knot, Infineon company in 1998 will surpass the junction device commercialization first and release the i.e. " CoolMOS of Superjunction VDMOS
TM", its P post is to adopt repeatedly the mode of extension and repeatedly ion injection to realize that CoolMOS has reduced conducting resistance significantly.
Avalanche energy is an important parameter weighing the power device reliability; The unlatching of the parasitic NPN transistor of Superjunction VDMOS is the main reason that causes this device snowslide to damage; Superjunction VDMOS is when application circuit turn-offs; To flow through when the inductive current in the circuit the is released base of parasitic NPN transistor is if base resistance is wide enough so that the base stage pressure drop surpasses the cut-in voltage of parasitic transistor, because parasitic transistor is in and amplifies the service area and electric current is a positive temperature coefficient; Cause the generation of local current concentration effect, and then cause the device local temperature to burn inefficacy above junction temperature.
Summary of the invention
The technical problem that the present invention solved provides the manufacture craft that a kind of avalanche energy that can improve Superjunction VDMOS device effectively promptly improves the low ultra junction device of shallow slot source electrode structure of reliability, the technology cost of device.
For solving above-mentioned technical problem, the technical scheme that the present invention takes:
The manufacture craft of the ultra junction device of a kind of shallow slot source electrode structure, its special character is: realize through following steps:
(1), growth N epitaxial loayer, deep etching and deep trouth extension filling formation P post then on the N+ substrate;
(2), the high temperature knot forms P type tagma to utilize P type tagma reticle mask to use more low-energy boron ion to inject also;
(3), after forming P type tagma, adopt the high-energy boron ion to use contact hole reticle mask to be infused in and form P+ district buried structure in the P type tagma;
(4), make fine and close gate oxide, polysilicon deposit and utilize polysilicon reticle mask etching to obtain polysilicon grating structure through dried oxygen technology;
(5), the arsenic ion of high concentration adopts polysilicon grating structure autoregistration injection, formation N+ source region;
(6), at polysilicon grating structure surface deposition BPSG dielectric layer, 950 ℃ of nitrogen atmosphere refluxed 30 minutes, and use contact hole reticle mask that the over etching of BPSG dielectric layer etching and silicon epitaxy layer is formed shallow slot;
(7), the upper surface deposit layer of aluminum of entire device, and utilize metal lithographic version mask etching aluminium to form source electrode and gate electrode, passivation, back face metalization forms drain electrode.
The P post also can be through extension repeatedly carries out long-time high temperature knot after repeatedly ion injects and forms in the step of above-mentioned manufacture craft (1).
The P post is through deep etching and carry out P type extension filling mode and prepare in the step of above-mentioned manufacture craft (1).
P type tagma employing boron ion implantation energy is 20 ~ 80KeV in the step of above-mentioned manufacture craft (2), and dosage is 1 * 10
15Cm
-2~ 9 * 10
15Cm
-2
P in the step of above-mentioned manufacture craft (3)
+It is 60 ~ 200KeV that district's buried structure adopts the boron ion implantation energy, and dosage is 2 * 10
15Cm
-2~ 2 * 10
16Cm
-2
N in the step of above-mentioned manufacture craft (5)
+It is 20 ~ 80KeV that the source region structure adopts phosphonium ion to inject energy, and dosage is 3 * 10
15Cm
-2~ 2 * 10
16Cm
-2
Compared with prior art, beneficial effect of the present invention:
The present invention has reduced the base length of parasitic NPN transistor, thereby has reduced base resistance, thereby has increased the difficulty that parasitic NPN transistor is opened, and has improved the avalanche energy of power device; Only need five reticle such as P post reticle, P type tagma reticle, polysilicon gate reticle, contact hole reticle and metal lithographic version,, saved N compared to the ultra junction device of routine
+Source region and P
+Distinguish two reticle, greatly reduce the technology cost of manufacture.
Description of drawings
Fig. 1 is a structural representation of the present invention;
Fig. 2 is a structural representation behind the epitaxy technique;
Fig. 3 is that the P post forms the back structural representation;
Fig. 4 is a structural representation after accomplish in P type tagma;
Fig. 5 is that the back structural representation is injected in the P+ district;
Fig. 6 is a structural representation after grid oxygen and the polygate electrodes etching;
Fig. 7 is that the back structural representation is injected in the autoregistration of N+ source region;
Fig. 8 be the deposit of BPSG dielectric layer and carry out the shallow slot etching after structural representation;
Fig. 9 is the metal deposit and anti-carves the structural representation that forms shallow slot source electrode.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is elaborated.
The present invention adopts the high-energy boron ion to use contact hole reticle mask to be infused in after P type tagma ion injects and forms P+ district buried structure in the P type tagma; Adopt more low-energy arsenic ion to carry out autoregistration after the polysilicon gate construction preparation and be infused in buried regions upside formation N+ source region, P+ district; Deposit BPSG dielectric layer adopts contact hole reticle mask to form contact hole and silicon is carried out over etching and forms shallow slot then, and break-through N+ source region also enters in the P+ district; Form the P+ district of U type; Thereby source metal electrode and N+ source region and P+ district all form good Ohmic contact, have reduced the base length of parasitic NPN transistor, thereby have reduced base resistance; Thereby increased the difficulty that parasitic NPN transistor is opened, improved the avalanche energy of power device.
Of the present invention through the following steps realization:
(1), growth N epitaxial loayer, deep etching and deep trouth extension filling formation P post then on the N+ substrate;
(2), the high temperature knot forms P type tagma to utilize P type tagma reticle mask to use more low-energy boron ion to inject also;
(3), after forming P type tagma, adopt the high-energy boron ion to use contact hole reticle mask to be infused in and form P+ district buried structure in the P type tagma;
(4), make fine and close gate oxide, polysilicon deposit and utilize polysilicon reticle mask etching to obtain polysilicon grating structure through dried oxygen technology;
(5), the arsenic ion of high concentration adopts polysilicon grating structure autoregistration injection, formation N+ source region;
(6), at polysilicon grating structure surface deposition BPSG dielectric layer, 950 ℃ of nitrogen atmosphere refluxed 30 minutes, and use contact hole reticle mask that the over etching of BPSG dielectric layer etching and silicon epitaxy layer is formed shallow slot;
(7), the upper surface deposit layer of aluminum of entire device, and utilize metal lithographic version mask etching aluminium to form source electrode and gate electrode, passivation, back face metalization forms drain electrode.
The P post can also be through extension repeatedly carries out long-time high temperature knot after repeatedly ion injects and forms in the step of above-mentioned manufacture craft (1).
The P post is through deep etching and carry out P type extension filling mode and prepare in the step of above-mentioned manufacture craft (1).
P type tagma employing boron ion implantation energy is 20 ~ 80KeV in the step of above-mentioned manufacture craft (2), and dosage is 1 * 10
15Cm
-2~ 9 * 10
15Cm
-2
P in the step of above-mentioned manufacture craft (3)
+It is 60 ~ 200KeV that district's buried structure adopts the boron ion implantation energy, and dosage is 2 * 10
15Cm
-2~ 2 * 10
16Cm
-2
N in the step of above-mentioned manufacture craft (5)
+It is 20 ~ 80KeV that the source region structure adopts phosphonium ion to inject energy, and dosage is 3 * 10
15Cm
-2~ 2 * 10
16Cm
-2
Contact hole reticle of the present invention has been used twice, is for the first time to form P+ district buried structure, is for the second time that etching BPSG dielectric layer forms contact hole and silicon is carried out over etching formation shallow slot.
Referring to Fig. 2, at the silicon monocrystalline substrate growing epitaxial layers, if adopt deep etching and extension fill process, can make P type tagma and the injection of JFET district ion this moment in epi-layer surface; Referring to Fig. 3, the P post can pass through deep etching and extension fill process, also can adopt repeatedly extension to reach repeatedly ion implantation technology; Referring to Fig. 4, P type tagma has identical symmetry axis with the P post; Referring to Fig. 5, utilize contact hole reticle mask to use the high-energy boron ion to inject and form P+ district buried structure; Referring to Fig. 6, utilize dried oxygen technology to make fine and close gate oxide, the polysilicon deposit also utilizes polysilicon reticle mask to obtain polysilicon grating structure; Referring to Fig. 7, the autoregistration ion that utilizes polysilicon grating structure to carry out the N+ source region injects; Referring to Fig. 8,, use contact hole reticle mask to realize the over etching of dielectric layer etching and silicon epitaxy layer is formed shallow slot at silicon chip surface deposit one deck BPSG dielectric layer; Referring to Fig. 9, depositing metal also anti-carves formation shallow slot source electrode structure.
Embodiment:
MOSFET with having super-junction structure explains, but the present invention is not limited to MOSFET.
One, in resistivity is the N epitaxial loayer of growth 45 μ m on the N+ silicon chip substrate of 0.001 Ω cm; The typical dopant concentrations of N epitaxial loayer is 1 * 1015cm-3; Use P post reticle mask to carry out deep etching then; Deep trouth is carried out extension fill formation P post, P post typical dopant concentrations is 2 * 1015cm-3.
Two, utilize P type tagma reticle mask, use 60KeV boron ion to inject, implantation dosage is 3 * 10
15Cm
-2
Three, utilize contact hole reticle mask to use the boron ion of 300KeV to inject and form P+ district buried regions, typical dopant concentrations is 1 * 10
19Cm
-3
Four, the thick gate oxide of dried oxide growth 100nm, the thick polysilicon of deposit 500nm, and etch polysilicon afterwards forms polysilicon gate construction.
Five, the arsenic ion of high concentration adopts the polysilicon grating structure autoregistration to inject, and ion implantation energy is 50KeV, forms the N+ source region, and typical dopant concentrations is 1020cm-3.
Six, the thick BPSG dielectric layer of deposit 2 μ m 950 ℃ of nitrogen atmosphere refluxed 30 minutes, and uses contact hole reticle mask that the over etching of BPSG dielectric layer etching and silicon epitaxy layer is formed shallow slot, and groove depth is about 0.4 μ m.
In the upper surface deposit layer of aluminum of entire device, and etching aluminium forms source electrode and gate electrode, passivation, back face metalization formation drain electrode.
Claims (6)
1. the manufacture craft of the ultra junction device of shallow slot source electrode structure is characterized in that: realize through following steps:
(1), growth N epitaxial loayer, deep etching and deep trouth extension filling formation P post then on the N+ substrate;
(2), the high temperature knot forms P type tagma to utilize P type tagma reticle mask to use more low-energy boron ion to inject also;
(3), after forming P type tagma, adopt the high-energy boron ion to use contact hole reticle mask to be infused in and form P+ district buried structure in the P type tagma;
(4), make fine and close gate oxide, polysilicon deposit and utilize polysilicon reticle mask etching to obtain polysilicon grating structure through dried oxygen technology;
(5), the arsenic ion of high concentration adopts polysilicon grating structure autoregistration injection, formation N+ source region;
(6), at polysilicon grating structure surface deposition BPSG dielectric layer, 950 ℃ of nitrogen atmosphere refluxed 30 minutes, and use contact hole reticle mask that the over etching of BPSG dielectric layer etching and silicon epitaxy layer is formed shallow slot;
(7), the upper surface deposit layer of aluminum of entire device, and utilize metal lithographic version mask etching aluminium to form source electrode and gate electrode, passivation, back face metalization forms drain electrode.
2. the manufacture craft of the ultra junction device of a kind of shallow slot source electrode structure according to claim 1 is characterized in that: the P post also can be through extension repeatedly carries out long-time high temperature knot after repeatedly ion injects and forms in the step of described manufacture craft (1).
3. the manufacture craft of the ultra junction device of a kind of shallow slot source electrode structure according to claim 1 is characterized in that: the P post is through deep etching and carry out P type extension filling mode and prepare in the step of described manufacture craft (1).
4. the manufacture craft of the ultra junction device of a kind of shallow slot source electrode structure according to claim 1 is characterized in that: P type tagma employing boron ion implantation energy is 20 ~ 80KeV in the step of described manufacture craft (2), and dosage is 1 * 10
15Cm
-2~ 9 * 10
15Cm
-2
5. the manufacture craft of the ultra junction device of a kind of shallow slot source electrode structure according to claim 1 is characterized in that: P in the step of described manufacture craft (3)
+It is 60 ~ 200KeV that district's buried structure adopts the boron ion implantation energy, and dosage is 2 * 10
15Cm
-2~ 2 * 10
16Cm
-2
6. the manufacture craft of the ultra junction device of a kind of shallow slot source electrode structure according to claim 1 is characterized in that: N in the step of described manufacture craft (5)
+It is 20 ~ 80KeV that the source region structure adopts phosphonium ion to inject energy, and dosage is 3 * 10
15Cm
-2~ 2 * 10
16Cm
-2
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103413764A (en) * | 2013-08-22 | 2013-11-27 | 上海宏力半导体制造有限公司 | Super junction power device and forming method thereof |
| CN103560086A (en) * | 2013-10-18 | 2014-02-05 | 西安龙腾新能源科技发展有限公司 | Super junction semiconductor device manufacturing method capable of improving avalanche capacity |
| CN106898555A (en) * | 2017-03-21 | 2017-06-27 | 西安龙腾新能源科技发展有限公司 | SJ MOS structures and its manufacture method with soft reverse recovery |
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| CN1433569A (en) * | 2000-06-02 | 2003-07-30 | 通用半导体公司 | Method of making power MOSFET |
| CN102104001A (en) * | 2009-12-18 | 2011-06-22 | 上海华虹Nec电子有限公司 | Method for improving breakdown voltage of trench type power MOS device |
| CN102479805A (en) * | 2010-11-30 | 2012-05-30 | 比亚迪股份有限公司 | Super junction semiconductor element and manufacture method thereof |
| CN102593157A (en) * | 2011-01-05 | 2012-07-18 | 茂达电子股份有限公司 | Power transistor with super interface of low miller capacitance and manufacturing method thereof |
-
2012
- 2012-08-17 CN CN201210292965.3A patent/CN102789990B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1433569A (en) * | 2000-06-02 | 2003-07-30 | 通用半导体公司 | Method of making power MOSFET |
| CN102104001A (en) * | 2009-12-18 | 2011-06-22 | 上海华虹Nec电子有限公司 | Method for improving breakdown voltage of trench type power MOS device |
| CN102479805A (en) * | 2010-11-30 | 2012-05-30 | 比亚迪股份有限公司 | Super junction semiconductor element and manufacture method thereof |
| CN102593157A (en) * | 2011-01-05 | 2012-07-18 | 茂达电子股份有限公司 | Power transistor with super interface of low miller capacitance and manufacturing method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103413764A (en) * | 2013-08-22 | 2013-11-27 | 上海宏力半导体制造有限公司 | Super junction power device and forming method thereof |
| CN103560086A (en) * | 2013-10-18 | 2014-02-05 | 西安龙腾新能源科技发展有限公司 | Super junction semiconductor device manufacturing method capable of improving avalanche capacity |
| CN103560086B (en) * | 2013-10-18 | 2016-08-31 | 西安龙腾新能源科技发展有限公司 | The preparation method of the super-junction semiconductor device of avalanche capacity can be improved |
| CN106898555A (en) * | 2017-03-21 | 2017-06-27 | 西安龙腾新能源科技发展有限公司 | SJ MOS structures and its manufacture method with soft reverse recovery |
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| CN102789990B (en) | 2015-10-28 |
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Address after: 710021 export processing zone, No. twelve, 1 road, Fengcheng, Shaanxi, Xi'an Patentee after: LONTEN SEMICONDUCTOR Co.,Ltd. Address before: 710021 export processing zone, No. twelve, 1 road, Fengcheng, Shaanxi, Xi'an Patentee before: XI'AN LONTEN RENEWABLE ENERGY TECHNOLOGY Inc. Address after: 710021 export processing zone, No. twelve, 1 road, Fengcheng, Shaanxi, Xi'an Patentee after: Longteng Semiconductor Co.,Ltd. Address before: 710021 export processing zone, No. twelve, 1 road, Fengcheng, Shaanxi, Xi'an Patentee before: LONTEN SEMICONDUCTOR Co.,Ltd. |